Vhld Based Cryptography

INTRODUCTION

Block cipher is an Encryption/Decryption scheme which breaks up the plain text/cipher text messages to be transmitted/received into strings (called blocks) of fixed length. It encrypts/decrypts one block at a time, thus all the transformations and operations must be executed over a byte or a set of bytes. The National Institute for Standards and Technology (NIST) selected the Rijndael algorithm as the official Advanced Encryption Standard (AES) in 2001 The AES cryptographic module will, most likely, replace the old Data Encryption Standard (DES) in all application and remain the reference in symmetric key ciphers for many years to come. The Rijndael algorithm has a simple structure and can be implemented efficiently on a wide range of microprocessors, in additional its operation is easy to defend against power and time attacks. A very important feature when a fast software module is needed and when the algorithm is coded for embedded platforms

Software implementation of AES algorithm is slower process (though easy). So the approach will be to present an FPGA implementation of AES algorithm. This Project shows the AES algorithm implemented on FPGA kit using Very High Speed Integrated Circuit Hardware Description language (VHDL). Xilinx software 11.1i version is used for simulation and optimization of the synthesizable VHDL code. All the transformations of both Encryptions and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. XC9500 CPLDs Family device are utilized for hardware evaluation. The focal approach of our design on hardware platform is to attain speed up (i.e. high throughput No. of block processed per second) at the same time, silicon area optimization.

THEORY

i.) WORKING PRINCIPLE

In cryptography, the Advanced Encryption Standard (AES), also known as Rijndael, is a block cipher adopted as an encryption standard by the US government.

AES has a fixed block size of 128 bits and a key size of 128, 192 or 256 bits, whereas Rijndael can be specified with key and block sizes in any multiple of 32 bits, with a minimum of 128 bits and a maximum of 256 bits. AES operates on a 4×4 array of bytes, termed the state. For encryption, each round of AES (except the last round) consists of four stages.

a) SubBytes - a non-linear substitution step where each byte is replaced with another according to a lookup table (known as S Box).

b) ShiftRows - a transposition step where each row of the state is shifted cyclically a certain number of steps.

c) MixColumns - a mixing operation