Advanced At-Speed Emulation Using Synopsys Haps Platform

Growing complexity and size of ASIC designs pose a great challenge to validate its functionality. Advancement in FPGA technologies in the past decade has enabled at-speed verification of multi-million gates SOCs through rapid prototyping.

Emulation of such complex design requires optimal design partitioning, high-speed interconnects, balanced clock and reset distribution and efficient debugging capabilities. To make this task more challenging validation of RF interface of such chips demands at-speed prototyping of the SOC.

This is where Synopsys's HAPS platform emerges as a savior to the Emulation Engineers.

HAPS's flexible interconnect design, low-skew clock distribution and modular architecture effectively implements at-speed prototypes.

With increasing complexity of SoC's (specifically Mobile platform) and squeezing time to mar-ket, requirement of different methods has grown rapidly to deliver quality SoC's in short span of time. Emulation is one of the most preferred methodologies to reduce the design cycle. Ad-vanced prototype platforms help in at-speed validation of design before tape-out and also enable early software development. This methodology dramatically reduces time-to-market for complex designs. These advanced prototype platforms also open up a window for architectural exploration along with validation.

Preference between a customized platform versus readily available platform requires an expert's insight. Decision to choose platform is driven by several factors: flexible connectivity between FPGA's and connecting off-shelf daughter cards, effortless movement of design across FPGA's, easiness in future expansion of the platform to name a few.

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