Digital Systems Lab

Lab Report 4 – Arithmetic Circuits

Lab Member 1: Tolulope Akiode (Student #: 8087786)

Lab Member 2: Maaz Irfan (Student #:7087724)

Course: ITI1100-B

Professor: Rami Abielmona

Due Date: March , 2015

Objectives

• A full adder is to be built in Quartus, and then test the outputs on the Altera UP-1 CPLD board. Verify that the expected matches the experimental results. This is Part I of the lab.

• Make the full adder built in Part I into a block diagram, and use it to create an 8 bit parallel adder/subtractor in Quartus.

• The third part’s objective was to create and simulate an overflow detector, however, as it was optional, we did not complete the objectives for the third part of the lab.

Equipment and Components used

• QUARTUS II 9.0 Web Edition Software

• Altera MAX EPM7128SLC84-7

• Altera UP-1 circuit board

• AC Adapter

• #22 solid-core wires

• Wire strippers

Circuit Diagrams

Circuit Diagram for Part I

Circuit Diagram for Part II

Comparison of expected data and experimental data

Part I

Expected Results:

Binary Inputs Carry Binary Sum Hex Equivalent

01111111 + 00000001 0 10000000 80

11111111 + 00000001 1 00000000 100

11000000 + 01000000