Facse: A Framework for Architecture and Compilation Space Exploration

To exploit microelectronics progresses for next processor generations, it is crucial to design new tools allowing a better adequacy between architectures and applications. The Facse project, which we present in this paper, strives to achieve this objective. As the two aspects of the system (hardware and software) are taken into account simultaneously, it is possible to increase the performances significantly. Facse is based on the use of adapted heuristics to guide search towards the most promising architecture and compiler optimization configurations in one side and rapid evaluation methods of these configurations on the other side.

The FACSE presented here, is a very ambitious project. Its concerns several domains: processor micro-architecture, compilation techniques, code optimization, and operational research. The contributions of this project are numerous. The tool that we propose to achieve COSE in the FACSE project can easily be integrated into different application development flows. COSE using FACSE can be useful in two

cases. In the first case, the application developer lacks of time and/or sufficient knowledge on the processor microarchitecture. In this case our tool will be integrated directly in the compiler and permits to obtain code with good performance. In the second case, the developer will simplify the work of the detailed analysis that he projects to make afterward. In this case the use of our tool can be considered as a preliminary phase for a detailed profiling phase (using for example VTune).

The utilization of the tools that we propose to develop for the DSE in FACSE is also very useful at different levels. The first application area concerns the design phase of future processors. The second application area concerns the utilization of these tools in platform customization such as in Application Specific Instruction set Processor (ASIP).