Electronics Xyz

EE311 Mini Project

Linear Feedback shift register

Team Members

Mangesh Joshi (11010245)                                                        Harsha Ranjan Kumar (11010229)
Kshitiz Joshi      (11010240)                                                        Amit Kumar                   (11010205)

Assingment : Linear Feedback Shift Register with feedback polynomial:

[pic 1]

1.  Verilog Code of the project
2.  Extraction of the Netlist from the Verilog file
3.  Layout generation from the netlist

What is an LFSR?

An LFSR is that shift register which, with clock, advances the signal through the register from one bit to the next most-significant bit.

The initial value of the LFSR is called the seed. The seed value is 10000000000000. When the outputs of the flip-flops are loaded with a seed value (anything except all 0s, which would cause the LFSR to produce all 0 patterns) and when the LFSR is clocked, it will generate a pseudorandom pattern of 1s and 0s. Note that the only signal necessary to generate the test patterns is the clock.

The two representations are Galois and Fibonacci representation.

We have used Fibonacci representation here.

[pic 2]

The bit positions that affect the next state are called the taps. In the diagram the taps are (2, 12, 13, 14). 

Given feedback polynomial has period 16383.

Applications:

 LFSR is used for generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences.

Verilog Code for the LFSR
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module LFSR(output reg[13:0] out,input clk);

reg r2,r12,r13,r14;
initial

        begin
        out[13:0]=14'b10000000000000;
        end

        always @(posedge clk)
        begin

        r2=out[1];
        r12=out[11];
        r13=out[12];
        r14=out[13];
              out[13:0]=out[13:0]<<1;
        out[0]=r2^r12^r13^r14;
        end

endmodule

Truth Table of XOR gates-This is timing diagram of XOR ofQ2, Q12, Q13 and Q14.

4[pic 3]

Net List Generated using Xilinx:-Gate level Netlist

[pic 4][pic 5][pic 6][pic 7][pic 8][pic 9][pic 10][pic 11][pic 12]

[pic 13]

Verilog Test Bench
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